CPU State

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Below is a list of parts of the CPU that hold a value in execution, The reader needs to include these into whatever class that represents the CPU.

(If your programming language requires defining as signed or unsigned, use unsigned)

A (accumulator, 8 bits) — main scratch register; target of most ALU operations.

X, Y (8 bits each) — index registers; used by indexed addressing modes and as loop counters.

PC (program counter, 16 bits) — address of the next byte to read. Split into PCL (low 8 bits) and PCH (high 8 bits); the cycle breakdowns refer to them separately when the CPU updates one half without the other.

SP (stack pointer, 8 bits) — low byte of the stack address. The stack lives in page 1, so the full address is 01:SP. Push decrements SP, pull increments it.

P (status register, 8 bits) — the flags:

bit 7 6 5 4 3 2 1 0
    N V - B D I Z C

N (negative), V (overflow), B (break — only meaningful in the stacked copy pushed by PHP/BRK), D (decimal — ignored by the 2A03), I (interrupt disable), Z (zero), C (carry).

IR (instruction register, 8 bits) — holds the opcode of the instruction currently executing. Loaded at cycle 1.

AD (effective address latch, 16 bits) — where the current instruction's operand address is assembled during addressing. Split into ADL (low) and ADH (high). The lo and hi you'll see in the mode breakdowns are ADL and ADH being written and later read as [ADH:ADL].

DL (data latch, 8 bits) — holds the most recent byte read from the bus; used to carry values between cycles.

"Fake" latches

The following latches exist in some form in the real hardware but are oversimplified here — though enough for accurate emulation. Include them too.

CL (carry latch, 1 bit) — remembers the page-crossing carry bit between the cycle that adds an index to the low address byte and the cycle that does the fixed-address re-read.

NEGATIVE (sign latch, 1 bit) — remembers the sign of a value across cycles, mainly for relative branches whose offset is negative.

IAL (intermediate ALU latch, 8 bits) — parks an ALU result between cycles so the next bus transaction can consume it.